The present invention concerns access of memory systems and pertains particularly to controlling the clock for memory accesses to synchronous devices in order to minimize power usage.
Clocked synchronous memory, such as synchronous static random access memory (SSRAM) and synchronous dynamic random access memory (SDRAM) utilize a free running clock (that is, the clock continues to run without interruption as long as power is applied to the system) in order to perform transfers of data. Each clocked synchronous memory accepts a free running clock signal on a clock input.
In order to limit power consumption, some SDRAM designs include a separate clock enable (CKE) pin. See, for example, Joint Electron Device Engineering Counsel (JEDEC) Standard No. 21-C Page 3.11.5-18. When the CKE pin is not enabled, the SDRAM is placed in a low power mode. When the CKE pin is not enabled, the free running clock signal continues to run. While placing the SDRAM in a low power mode reduces the power consumption of the SDRAM, generally at least one clock cycle is required to return the SDRAM to normal operation after the SDRAM has been placed into the low power mode. This introduces a latency in operation of the SDRAM which has a negative impact on performance. In addition to the latency introduced by use of the CKE pin, there is also the disadvantage that such a system requires logic to control the CKE pin.